1. Field of the Invention
The present invention relates to data communications, and more particularly to a low power serial link.
2. Art Background
Continuing advances in consumer electronics and computing technologies are driving the need for high-speed communications links between silicon chips. While high-speed links have been traditionally used in network switching, as described by “Clause 47: XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI)”, Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE 802.3ae, August 2002; and in high-performance computing applications, as described by PCI Express Base Specification Revision 1.0a, PCI-SIG, April 2003, there is an increasing need for high-speed links in mobile consumer electronic devices. For example, in mobile phones there is a need for communication between the digital signal processor (DSP) and the liquid crystal display (LCD) driver chip and between the DSP and the camera module. With improvements in the resolution (i.e. number of pixels) in the LCD and camera comes a need for increased data rates in the chip-to-chip links.
High-speed chip-to-chip communications can be performed using many parallel input and output (I/O) drivers each operating at a relatively slow rate or using a small number of I/O drivers operating at a higher rate. In general the number of pads available on a chip for high-speed chip-to-chip communication is limited by a host of factors including package size, requirements for power supply pads, and printed circuit board space. In portable electronics applications, where space is at a premium, the use of faster links with fewer lines is advantageous. Thus, serial-type architectures are increasingly being used in such devices.
Further, low power dissipation is desirable in most electronics applications because it reduces the need for heat dissipation and cases power supply design. However, power is especially important in mobile applications, where battery life must be maximized and battery weight minimized. Internal communications structures can be a major source of power dissipation, thus, low power chip-to-chip links are especially desirable in mobile applications.
Hence, a low power serial structure with low power dissipation and a small footprint is a desirable internal communications structure for a portable device. A number of conventional designs attempt to provide such a structure, but each has several drawbacks.
For instance, a block diagram of a conventional low-power serial receiver/transmitter pair is shown in FIGS. 1A and 1B. This pair is representative of the link embodied in a Fairchild Semiconductor device described in “FIN12AC μSerDes Low Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges”, Fairchild Semiconductor Corporation Datasheet.
In the transmit portion 100a, input data, “Parallel Tx Data”, to be transmitted on the serial link are fed into a multiplexer (MUX) 110 and then driven off-chip by an output driver circuit 112 to produce an output signal “Tx Signal”. Clocks required by MUX 110 are generated using a phase-locked loop (PLL) 120. A transmit clock is driven along with the data by a separate clock driver circuit 122. The clock, “Tx clock” provides timing to the receiver at the other end of the link. The data is usually driven using binary, non-return-to-zero (NRZ) signaling as shown in FIG. 2. While binary, single-ended signaling is shown, combinations of differential signaling and multi-level signaling can also be used.
In the receiver portion 100b, the “Tx Signal” is received as “Rx Signal” and the “Tx Clock” is received as “Rx Clock”. The “Rx Signal” is retimed using “Rx Clock”. A data receiver circuit 132 receives the “Rx Signal” and a clock receiver circuit 134 receives the “Rx Clock”. A retiming circuit 130 then retimes the “Rx Signal” data using the “Rx Clock”, and provides the retimed data to an output de-multiplexer (DeMUX) 140. The DeMUX 140 uses the received clock to present the data in a low speed (relative to the serial link speed), parallel format as “Parallel Rx Data”.
With the use of the architecture in FIGS. 1A and 1B, two signals (clock and data) have to be routed in each direction, resulting in a power dissipation and printed circuit board area penalty.
A second conventional serial link architecture is shown in FIGS. 3A and 3B. This architecture is representative of the transmitter and receiver pair described in “THCV213 and THCV214 LVDS SerDes Transmitter and Receiver”, THine Electronics Datasheet.
In this architecture the transmitter does not send a clock along with the data. In the transmit portion 200a, input data, “Parallel Tx Data”, to be transmitted on the serial link are fed into a multiplexer (MUX) 210 and then driven off-chip by an output driver circuit 212 to produce an output signal “Tx Signal”. Clocks required by MUX 210 are generated using a phase-locked loop (PLL) 220. No transmit clock is driven along with the data. Instead, timing is recovered at the receiver.
In the receiver portion 200b, the “Tx Signal” is received as “Rx Signal”. A data receiver circuit 232 receives the “Rx Signal”. A clock-and-data recovery (CDR) circuit 250, which is a specialized form of PLL, is used to recover a clock that is synchronous with the received serial data signal “Rx Signal”. The recovered clock from the CDR 250 is provided to both the retiming circuit 230 and to the output de-multiplexer (DeMUX) 240. The retiming circuit 230 uses the recovered clock to retime the input data and provides the retimed data to the output DeMUX 240. The output DeMUX 240 also receives the recovered clock and uses the clock to present the received data in a low speed (relative to the serial link speed), parallel format as “Parallel Rx Data”.
In FIGS. 3A and 3B, the elimination of the transmit clock driver results in power savings. However a CDR is generally expensive in terms of power dissipation and chip area, as described in, Y. Greshishchev et al, “A Fully-Integrated SiGe Receiver IC for 10 Gb/s Data Rate”, IEEE Journal of Solid-State Circuits, December 2000. Furthermore, with NRZ signaling the CDR is implemented using a control loop that is, in general, complicated to design. A tradeoff must be made among the following factors: (1) tracking capability of the CDR in the presence of input signal phase jitter, (2) CDR loop stability, and (3) the variation of CDR loop dynamics over variations in the integrated circuit manufacturing process, power supply voltage, and chip temperature.